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a63l73321 series 128k x 32 bit synchronous high speed sram preliminary with burst counter and flow-through data output preliminary (december , 1998, version 0.0) amic technology, inc. document title 128k x 32 bit synchronous high speed sram with burst counter and flow- through data output revision history rev. no. history issue date remark 0.0 initial issue december 14, 1998 preliminary 0.1 change fast access times from 8.5/9.5/10 ns to 9.5/10/12 ns june 9, 1999 change i cc1 from 300ma to 350ma(max.)
a63l73321 series 128k x 32 bit synchronous high speed sram preliminary with burst counter and flow-through data output preliminary (june , 1999, version 0.1) 1 amic technology, inc. features n fast access times: 9.5/10/12 ns n single +3.3v+10% or +3.3v-5% power supply n synchronous burst function n individual byte write control and global write n three sepa rate chip enables allow wide range of options for ce control, address pipelining n selectable burst mode n sleep mode (zz pin) provided n available in 100-pin lqfp package general description the a63l73321 is a high-speed, low-power sram containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. the a63l73321 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128k x 32 sram core to provide a wide range of data ram applications. the positive edge triggered single clock input (clk) controls all synchronous inputs passing through the registers. synchronous inputs include all addresses (a0 - a16), all data inputs (i/o 1 - i/o 32 ), active low chip enable ( ce ), two additional chip enables (ce2, ce2 ), burst control inputs ( adsc , adsp , adv ), byte write enables ( bwe , bw1 , bw2 , bw3 , bw4 ) and global write ( gw ). asynchronous inputs include output enable ( oe ), clock (clk), burst mode (mode) and sleep mode (zz). burst operations can be initiated with either the address status processor ( adsp ) or address status controller ( adsc ) input pin. subsequent burst sequence burst addresses can be internally generated by the a63l73321 and controlled by the burst advance ( adv ) pin. write cycles are internally self-timed and synchronous with the rising edge of the clock (clk). this feature simplifies the write interface. individual byte enables allow individual bytes to be written. bw1 controls i/o 1 - i/o 8 , bw2 controls i/o 9 - i/o 16 , bw3 controls i/o 17 - i/o 24 , and bw4 controls i/o 25 - i/o 32 , all on the condition that bwe is low. gw low causes all bytes to be written.
a63l73321 series preliminary (june, 1999, version 0.1) 2 amic technology, inc. pin configuration nc i/o 17 i/o 18 vccq gndq i/o 19 i/o 20 i/o 21 i/o 22 gndq i/o 23 i/o 24 vccq vcc nc i/o 31 gnd i/o 25 i/o 26 vccq gndq i/o 27 i/o 28 i/o 29 i/o 30 gndq vccq i/o 32 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc i/o 16 i/o 15 vccq gndq i/o 14 i/o 13 i/o 12 i/o 11 gndq vccq i/o 10 i/o 9 gnd nc vcc zz i/o 8 i/o 7 vccq gndq i/o 6 i/o 5 i/o 4 i/o 3 gndq vccq i/o 2 i/o 1 nc 50 49 48 47 46 45 44 43 42 40 41 39 38 37 36 35 34 33 32 31 a16 a15 a14 a13 a12 a11 a10 nc nc vcc gnd nc nc a0 a1 a2 a3 a4 a5 mode 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ce2 a7 a6 clk gnd vcc a9 a8 a63l73321 nc adv adsp adsc oe bwe gw ce2 bw1 bw2 bw3 bw4 ce
a63l73321 series preliminary (june, 1999, version 0.1) 3 amic technology, inc. block diagram mode logic clk logic address registers burst logic address counter clr byte write enable logic byte1 write driver byte2 write driver byte3 write driver byte4 write driver 8 8 8 8 128kx8x4 memory array 8 8 8 8 32 output buffer data-in registers 4 chip enable logic output enable logic 4 32 17 zz mode adv clk adsc adsp a0-a16 gw bwe bw1 bw2 bw3 bw4 ce ce2 ce2 oe i/o 1 - i/o 32
a63l73321 series preliminary (june, 1999, version 0.1) 4 amic technology, inc. pin description pin no. symbol description 32 - 37, 44 - 50, 81, 82, 99, 100 a0 - a16 address inputs 89 clk clock 87, 93 - 96 bwe , bw1 - bw4 byte write enables 88 gw global write 86 oe output enable 92, 97, 98 ce2 ,ce2, ce chip enables 83 adv burst address advance 84 adsp processor address status 85 adsc controller address status 31 mode burst mode: high or nc (interleaved burst) low (linear burst) 64 zz asynchronous power-down (snooze): high (sleep) low or nc (wake up) 2, 3, 6 - 9, 12, 13, 18, 19, 22 - 25, 28, 29, 52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79 i/o 1 - i/o 32 data inputs/outputs 1, 14, 16, 30, 38, 39, 42, 43, 51, 66, 80 nc no connection 15, 41, 65, 91 vcc power supply 17, 40, 67, 90 gnd ground 4, 11, 20, 27, 54, 61, 70, 77 vccq isolated output buffer supply 5, 10, 21, 26, 55, 60, 71, 76 gndq isolated output buffer ground
a63l73321 series preliminary (june, 1999, version 0.1) 5 amic technology, inc. synchronous truth table (see notes 1 through 5) operation address used ce ce2 ce2 adsp adsc adv write oe clk i/o operation deselected cycle, power-down none h x x x l x x x l-h high-z deselected cycle, power-down none l x l l x x x x l-h high-z deselected cycle, power-down none l h x l x x x x l-h high-z deselected cycle, power-down none l x l h l x x x l-h high-z deselected cycle, power-down none l h x h l x x x l-h high-z read cycle, begin burst external l l h l x x x l l-h dout read cycle, begin burst external l l h l x x x h l-h high-z write cycle, begin burst external l l h h l x l x l-h din read cycle, begin burst external l l h h l x h l l-h dout read cycle, begin burst external l l h h l x h h l-h high-z read cycle, continue burst next x x x h h l h l l-h dout read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h dout read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h din write cycle, continue burst next h x x x h l l x l-h din read cycle, suspend burst current x x x h h h h l l-h dout read cycle, suspend burst current x x x h h h h h l-h high-z read cycle, suspend burst current h x x x h h h l l-h dout read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h din write cycle, suspend burst current h x x x h h l x l-h din
a63l73321 series preliminary (june, 1999, version 0.1) 6 amic technology, inc. notes: 1. x = "disregard", h = logic high, l = logic low. 2. write = l means: 1) any bwx ( bw1 , bw2 , bw3 , or bw4 ) and bwe are low or 2) gw is low. 3. all inputs except oe must be synchronized with setup and hold times around the rising edge (l-h) of clk. 4. for write cycles that follow read cycles, oe must be high before the input data request setup time and held high throughout the input data hold time. 5. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. refer to the write timing diagram for clarification. write truth table operation gw bwe bw1 bw2 bw3 bw4 read h h x x x x read h l h h h h write byte 1 h l l h h h write all bytes h l l l l l write all bytes l x x x x x
a63l73321 series preliminary (june, 1999, version 0.1) 7 amic technology, inc. linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (mode = high or nc) first address (external) second address (internal) third address (internal) fourth address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00 absolute maximum ratings* power supply voltage (vcc) . . . . . . . . . . -0.5v to +4.6v voltage relative to gnd for any pin except vcc (vin, vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vcc +0.5v power dissipation (p d ) . . . . . . . . . . . . . . . . . . . . . . . . 2w operating temperature ( topr) . . . . . . . . . . . 0 c to 70 c storage temperature ( tbias) . . . . . . . . . . -10 c to 85 c storage temperature ( tstg) . . . . . . . . . . . -55 c to 125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (0 c t a 70 c, vcc, vccq = 3.3v+10% or 3.3v-5%, unless otherwise noted) symbol parameter min. typ. max. unit note vcc supply voltage (operating voltage range) 3.135 3.3 3.6 v vccq isolated input buffer supply 3.135 3.3 vcc v gnd supply voltage to gnd 0.0 - 0.0 v v ih input high voltage 2.0 - vcc+0.3 v 1, 2 v ihq input high voltage (i/o pins) 2.0 - vcc+0.3 v v il input low voltage -0.3 - 0.8 v 1, 2
a63l73321 series preliminary (june, 1999, version 0.1) 8 amic technology, inc. dc electrical characteristics (0 c t a 70 c, vcc, vccq = 3.3v+10% or 3.3v-5%, unless otherwise noted) symbol parameter min. max. unit test conditions note ? i li ? input leakage current - 2.0 m a all inputs v in = gnd to vcc ? i lo ? output leakage current - 2.0 m a oe = v ih , vout = gnd to vcc i cc1 supply current - 350 ma device selected ; vcc = max. iout = 0ma, all inputs = v ih or v il cycle time = t kc min. 3, 11 i sb1 standby current - 25 ma device deselected ; vcc = max. all inputs are fixed. all inputs 3 vcc - 0.2v or gnd + 0.2v cycle time = t kc min. 11 i sb2 - 10 ma zz 3 vcc - 0.2v v ol output low voltage - 0.4 v i ol = 8 ma v oh output high voltage 2.4 - v i oh = -4 ma capacitance symbol parameter typ. max. unit conditions c in input capacitance 3 4 pf t a = 25 c; f = 1mhz c i/o input/output capacitance 4 5 pf vcc = 3.3v * these parameters are sampled and not 100% tested.
a63l73321 series preliminary (june, 1999, version 0.1) 9 amic technology, inc. ac characteristics (0 c t a 70 c, vcc = 3.3v+10% or 3.3v-5%) symbol parameter -9.5 -10 -12 unit note min. max. min. max. min. max. t kc clock cycle time 10 - 11 - 12 - ns t kh clock high time 4.0 - 4.0 - 4.0 - ns t kl clock low time 4.0 - 4.0 - 4.0 - ns t kq clock to output valid - 9.5 - 10 - 12 ns t kqx clock to output invalid 3.0 - 3.0 - 3.0 - ns t kqlz clock to output in low-z 4.0 - 4.0 - 4.0 - ns 5, 6 t kqhz clock to output in high-z - 5.0 - 5.0 - 5.0 ns 5, 6 t oeq oe to output valid - 5.0 - 5.0 - 5.0 ns 8 t oelz oe to output in low-z 0 - 0 - 0 - ns 5, 6 t oehz oe to output in high-z - 5.0 - 5.0 - 5.0 ns 5, 6 setup times t as address 2.0 - 2.0 - 2.5 - ns 7, 9 t adss address status ( adsc , adsp ) 2.0 - 2.0 - 2.5 - ns 7, 9 t advs address advance ( adv ) 2.0 - 2.0 - 2.5 - ns 7, 9 t ws write signals ( bw1 , bw2 , bw3 , bw4 , bwe , gw ) 2.0 - 2.0 - 2.5 - ns 7, 9 t ds data-in 2.0 - 2.0 - 2.5 - ns 7, 9 t ces chip enable ( ce , ce2, ce2 ) 2.0 - 2.0 - 2.5 - ns 7, 9
a63l73321 series preliminary (june, 1999, version 0.1) 10 amic technology, inc. ac characteristics (continued) symbol parameter -9.5 -10 -12 unit note min. max. min. max. min. max. hold times t ah address 0.5 - 0.5 - 0.5 - ns 7, 9 t adsh address status ( adsc , adsp ) 0.5 - 0.5 - 0.5 - ns 7, 9 t aah address advance ( adv ) 0.5 - 0.5 - 0.5 - ns 7, 9 t wh write signal ( bw1 , bw2 , bw3 , bw4 , bwe , gw ) 0.5 - 0.5 - 0.5 - ns 7, 9 t dh data-in 0.5 - 0.5 - 0.5 - ns 7, 9 t ceh chip enable ( ce , ce2, ce2 ) 0.5 - 0.5 - 0.5 - ns 7, 9 notes: 1. all voltages refer to gnd. 2. overshoot: v ih +4.6v for t t kc /2. undershoot: v ih 3 -0.7v for t t kc /2. power-up: v ih +3.6 and vcc 3.1v for t 200ms 3. i cc1 is given with no output current. i cc1 increases with greater output loading and faster cycle times. 4. test conditions assume the output loading shown in figure 1, unless otherwise specified. 5. for output loading, c l = 5pf, as shown in figure 2. transition is measured 150mv from steady state voltage. 6. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t qelz . 7. a write cycle is defined by at least one byte write enable low and adsp high for the required setup and hold times. a read cycle is defined by all byte write enables high and ( adsc or adv low) or adsp low for the required setup and hold times. 8. oe has no effect when a byte write enable is sampled low. 9. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when either adsp or adsc is low and the chip is enabled. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when eithe r adsp or adsc is low to remain enabled. 10. the load used for v oh , v ol testing is shown in figure 2. ac load current is higher than the given dc values. ac i/o curves are available upon request. 11. "device deselect ed" means device is in power-down mode, as defined in the truth table. "device selected" means device is active (not in power-down mode). 12. mode pin has an internal pulled-up, and zz pin has an internal pulled-down. all of then exhibit an input leakage current of 10 m a. 13. snooze (zz) input is recommended that users plan for four clock cycles to go into sleep mode and four clocks to emerge from sleep mode to ensure no data is lost.
a63l73321 series preliminary (june, 1999, version 0.1) 11 amic technology, inc. timing waveforms read timing notes: 1. qa(2) refers to output from address a2. q(a2+1) refers to output from the next internal burst address following a2. 2. ce and ce2 have timing identical to ce . on this diagram, when ce is low, ce2 is low and ce2 is high. when ce is high, ce2 is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. oe does not cause q to be driven until after the following clock rising edge. 4. outputs are disabled t kqhz after deselect. clk adsp adsc address a1 a2 gw,bwe bw1-bw4 ce (note 2) adv oe q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) high-z dout (note 3) t oehz t kqx t kq burst wraps around to its initial state t kqhz burst read deselect cycle (note 4) adv suspends burst t advh t advs t ceh t ces t wh t ws t ah t as t adsh t adss t adsh t adss t kl t kh t kc q(a2+2) (note *1) t oeq t kqlz t kq t oelz single read don't care undefined
a63l73321 series preliminary (june, 1999, version 0.1) 12 amic technology, inc. timing waveforms (continued) clk adsp adsc address a1 a2 a3 oe d(a2) d(a2+1) d(a2+2) d(a2+3) d(a3) d(a3+1) high-z din t ah t as t adsh t adss t adsh t adss t kl t kh t kc t adsh t adss adsc extends burst gw ce (note 2) adv d(a1) d(a2+1) d(a3+2) dout burst read single write extended burst write t oehz t dh t ds (note 3) (note 4) adv suspends burst t advh t advs t ceh t ces t wh t ws byte write signals are ignored for first cycle when adsp initiates burst t wh t ws bwe,bw1-bw4 (note 5) (note 1) don't care undefined write timing notes: 1. d(a2) refers to output from address a2. d(a2+1) refers to output from the internal burst address immediately following a2. 2. timing for ce2 and ce2 is identical to that for ce . as shown in the above diagram, when ce is low, ce2 is low and ce2 is high. whe n ce is high, ce2 is high and ce2 is low. 3. oe must be high before the input data setup, and held high throughout the data hold period. this prevents input/output data contention for the pe riod prior to the time byte write enable inputs are sampled. 4. adv must be high to permit a write to the loaded address. 5. byte write enables are decided by means of a write truth table.
a63l73321 series preliminary (june, 1999, version 0.1) 13 amic technology, inc. timing waveforms (continued) read/write timing notes: 1. q(a4) refers to output from address a4. q(a4+1) refers to output from the next internal burst address following a4. 2. ce2 and ce2 have timing identical to ce . on this diagram, when ce is low, ce is low and ce2 is high, when ce is high, ce2 is high and ce2 is low. 3. the data bus (q) remains in high-z following a write cycle unless an adsp , adsc , or adv cycle is performed. 4. byte write enables are decided by means of a write truth table. 5. back-to-back reads may be controlled by either adsp or adsc clk adsp adsc address a1 a3 ce (note 2) adv oe d(a3) d(a5) d(a6) high-z din t ceh t ces t adsh t adss t kl t kh t kc a2 a4 a5 a6 gw,bwe, bw1-bw4 (note 3) q(a1) q(a2) q(a4) q(a4+1) dout back-to-back reads single write burst read back-to-back writes (note 1) t kq t oelz t dh t ds t ws t wh t as t ah q(a4+2) q(a4+3) t oehz t kq don't care undefined
a63l73321 series preliminary (june, 1999, version 0.1) 14 amic technology, inc. ac test conditions input pulse levels gnd to 3v input rise and fall times 1.5ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 z o =50 w q r l =50 w v t =1.5v figure 1. output load equivalent 350 w q +3.3v 320 w 5pf figure 2. output load equivalent
a63l73321 series preliminary (june, 1999, version 0.1) 15 amic technology, inc. ordering information part no. access times (ns) package a63l73321e-9.5 9.5 100l lqfp A63L73321E-10 10 100l lqfp a63l73321e-12 12 100l lqfp
a63l73321 series preliminary (june, 1999, version 0.1) 16 amic technology, inc. package information lqfp 100l outline dimensions unit: inches/mm symbol dimensions in inches dimensions in mm min. nom. max. min. nom. max. a 1 0.002 - - 0.05 - - a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.011 0.013 0.015 0.27 0.32 0.37 c 0.005 - 0.008 0.12 - 0.20 h e 0.860 0.866 0.872 21.85 22.00 22.15 e 0.783 0.787 0.791 19.90 20.00 20.10 h d 0.624 0.630 0.636 15.85 16.00 16.15 d 0.547 0.551 0.555 13.90 14.00 14.10 e 0.026 bsc 0.65 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref y - - 0.004 - - 0.1 q 0 3.5 7 0 3.5 7 notes: 1. dimen sions d and e do not include mold protrusion. 2. dimensions b does not include dambar protrusion. total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. 31 50 51 80 81 100 h d d e h e 1 30 b d y a 1 a 2 l 1 c e q l

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